Open CPU / SoC design, all the way up to Debian (37c3)

This lecture will cover many aspect of designing a RISC-V CPU, out-of-order execution, multi-core, memory coherency, security and running linux and debian on a FPGA. This will be based on the recently developped NaxRiscv core, a free and opensource RISC-V softcore. I will cover many interresting aspect of the project/flow to provide a overview of many technical aspect in such project : - Hardware description languages - CPU design - Information leak (spectre) - Memory coherency - Linux / Debian requirements - Debugging / Simulation about this event: https://events.ccc.de/congress/2023/hub/event/open_cpu_soc_design_all_the_way_up_to_debian/